View STAP16DPS05_8794114.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. november 2015 docid024315 rev 6 1/34 STAP16DPS05 low voltage 16-bit constant current led sink driver with output error detection and auto power-saving for automotive applications datasheet - production data features ? aecq100 qualification ? low voltage power supply down to 3 v ? 16 constant current output channels ? adjustable output current through external resistor ? short and open output error detection ? serial data in/parallel data out ? 3.3 v micro driver-able ? output current: 5-100 ma ? auto power-saving ? max. clock frequency: 30 mhz ? 20 v current generator rated voltage ? power supply voltage: from 3 v to 5.5 v ? thermal shutdown for overtemperature protection ? esd protection 2.0 kv hbm applications ? dashboard and infotainment backlighting ? exterior/interior lighting ? dtrls description the STAP16DPS05 is a monolithic, low voltage, low current power 16-bit shift register designed for led panel displays. the device contains a 16-bit serial-in, parallel-out shift register that feeds a 16- bit d-type storage register. in the output stage, sixteen regulated current sources are designed to provide 5-100 ma constant current to drive the leds. the STAP16DPS05 features the open and short led detections on the outputs.the STAP16DPS05 ensures the backward compatibility with the stp16c/l596. the detection circuit checks 3 different conditions, which can occur on the output line: short to gnd, short to v o or open line. the data detection results are loaded in the shift register and shifted out via the serial line output. the detection functionality is implemented without increasing the pin number. through a secondary function of the output enable and latch pin (dm1 and dm2 respectively), a dedicated logic sequence allows the device to enter or leave detection mode. through an external resistor, users can adjust the output current of the STAP16DPS05, thus controlling the light intensity of the leds. in addition, the user can adjust the intensity of the brightness of the leds from 0% to 100% through the oe/dm2 pin. the STAP16DPS05 guarantees a 20 v output driving capability, allowing users to connect more leds in series. the high clock frequency, 30 mhz, also satisfies the system requirement of high volume data transmission. the 3.3 v of voltage supply is very useful for applications that interface any microcontroller from 3.3 v micro. compared with a standard tssop package, the tssop exposed pad increases the capability of heat dissipation by a factor of 2.5. +76623 h[srvhgsdg table 1. device summary order code package packing STAP16DPS05xttr htssop24 (exposed pad) 2500 parts per reel www.st.com
contents STAP16DPS05 2/34 docid024315 rev 6 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin connections and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 phase one: ?entering in detection mode? . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 phase two: ?error detection? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 phase three: ?resuming to normal mode? . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 tssop24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 29 8.2 tssop24 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . . 31 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
docid024315 rev 6 3/34 STAP16DPS05 list of tables 34 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. typical current accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 6. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 7. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 8. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 9. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. output current-r ext resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. iset vs. dropout voltage (vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. entering in detection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. iodec average value at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. iodec average value at 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. tssop24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. tssop24 exposed pad tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of figures STAP16DPS05 4/34 docid024315 rev 6 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. oe/dm2 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. le/dm1 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. clk, sdi terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. sdo terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. clock, serial-in, serial-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. clock, serial-in, latch, enable, outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. output current-r ext resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. iset vs. dropout voltage (vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. idd on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. entering in detection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15. detection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16. timing example for open and/or short detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. resuming to normal mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. error detection sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. error detection typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 21. auto power-saving feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 22. delay le-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 23. auto power-saving behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 24. tssop24 exposed pad package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 25. tssop24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid024315 rev 6 5/34 STAP16DPS05 summary description 34 1 summary description 1.1 pin connections and description figure 1. pin connections note: the exposed pad is electrically connected to a metal layer electrically isolated or connected to ground. table 2. typical current accuracy output voltage current accuracy output current v dd temperature between bits between ics 1.3 v 1.5% 5% 20 to 100 ma 3.3 v to 5 v 25 c table 3. pin description pin n symbol name and function 1 gnd ground terminal 2 sdi serial data input terminal 3 clk clock input terminal 4 le/dm1 latch input terminal - detect mode 1 (see operation principle) 5-20 out-15 output terminal 21 oe/dm2 input terminal of output enable (active low) - detect mode 1 (see operation principle) 22 sdo serial data out terminal 23 r-ext input terminal of an external resistor for constant current programing 24 v dd supply voltage terminal
electrical ratings STAP16DPS05 6/34 docid024315 rev 6 2 electrical ratings 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. . 2.2 thermal data table 4. absolute maximum ratings symbol parameter value unit v dd supply voltage 0 to 7 v v o output voltage -0.5 to 20 v i o output current 100 ma v i input voltage -0.4 to v dd v i gnd gnd terminal current 1600 ma f clk clock frequency 50 mhz t opr operating temperature range -40 to +150 c t stg storage temperature range -55 to +150 c table 5. thermal data symbol parameter value unit r th(ja) thermal resistance junction-ambient (1) 1. according to jedec standard 51-7b. tssop24 (2) exposed pad 2. the exposed pad should be soldered to the pc b in order to derive the thermal benefits. 37.5 c/w
docid024315 rev 6 7/34 STAP16DPS05 electrical ratings 34 2.3 recommended operating conditions table 6. recommended operating conditions symbol parameter test conditions min. typ. max. unit v dd supply voltage 3.0 - 5.5 v v o output voltage - 20 v i o output current outn 5 - 100 ma i oh output current serial-out - +1 ma i ol output current serial-out - -1 ma v ih input voltage 0.7 v dd -v dd +0.3 v v il input voltage -0.3 - 0.3 v dd v t wlat le/dm1 pulse width v dd = 3.0 v to 5.0 v 6- ns t wclk clk pulse width 8 - ns t wen oe/dm2 pulse width 100 - ns t setup(d) setup time for data 10 - ns t hold(d) hold time for data 5 - ns t setup(l) setup time for latch 10 - ns f clk clock frequency cascade operation (1) 1. if the device is connected in cascade, it may not be possible to achieve the maximum data transfer. please consider the timings carefully. -30mhz
electrical characteristics STAP16DPS05 8/34 docid024315 rev 6 3 electrical characteristics v dd = 5v, t j = -40 c to 125 c, unless otherwise specified. table 7. electrical characteristics symbol parameter test conditions min. typ. max. unit v ih input voltage high level 0.7v dd v dd v v il input voltage low level gnd 0.3v dd v ol serial data output voltage (sdo) i ol = + 1 ma 0.03 0.4 v oh i oh = - 1 ma v dd -0.4 i oh output leakage current vo =19 v, outn = off 0.5 2 a ? i ol1 current accuracy channel- to-channel (1) (2) v dd = 3.3 v, v o = 0.4 v, r ext = 980 ? 1.5 5 % ? i ol2 v dd = 3.3 v, v o = 1.3 v, r ext = 200 ? 1.2 4 ? i ol3 current accuracy device-to- device (1) v dd = 3.3 v, v o = 0.4 v, r ext = 980 ? 6 ? i ol4 v dd = 3.3 v, v o = 1.3 v, r ext = 200 ? 6 r in (up) pull-up resistor for oe pin 150 300 600 k ? r in (down) pull-down resistor for le pin 100 200 400 idd(autooff) supply current (off) r ext = 980 ? , oe = low, out0 to out7 = off 200 300 a idd(off1) r ext = 980 ? , oe = high, out0 to out7 = on 58 ma idd(off2) r ext = 200 ? , oe = high, out0 to out15 = on 13 20 idd(on1) supply current (on) r ext = 980 ? , oe = low, out0 to out15 = on 68 idd(on2) r ext = 200 ? , oe = low, out0 to out15 = on 13 20 tsd thermal shutdown (3) 170 c 1. test performed with all outputs turned on, but only one output loaded at a time. 2. d iol + = ((i olmax - i olmean )/ i olmean )*100, d iol - = ((i olmin - i olmean )/ i olmean )*100, where i olmean = (i olout1 +i olout2 +?+i olout16 ) / 16. 3. not tested, guaranteed by design.
docid024315 rev 6 9/34 STAP16DPS05 electrical characteristics 34 3.1 switching characteristics v dd = 5 v, t j = 25 c, unless otherwise specified. table 8. switching characteristics (1)(2) symbol parameter test conditions min. typ. max. unit f clk clock frequency cascade operation 30 mhz tplh1 clk-outn le\dm1 = h oe\dm2 = l propagation delay time (?l? to ?h?) vih = vdd vil = gnd cl = 10 pf io = 20 ma vl = 3 v r ext = 1 k rl = 60 v dd = 3.3 v 40 45 ns v dd = 5 v 20 45 tplh2 le\dm1-outn oe\dm2 = l v dd = 3.3 v 51 80 ns v dd = 5 v 32 50 tplh3 oe\dm2-outn le\dm1 = h v dd = 3.3 v 50 80 ns v dd = 5 v 30 50 tplh clk - sdo v dd = 3.3 v 22 35 ns v dd = 5 v 15 25 tphl1 clk-outn le\dm1 = h oe\dm2 = l propagation delay time (?h? to ?l?) v dd = 3.3 v 15 25 ns v dd = 5 v 12 20 tphl2 le\dm1-outn oe\dm2 = l v dd = 3.3 v 13 25 ns v dd = 5 v 10 15 tphl3 oe\dm2-outn le\dm1 = h v dd = 3.3 v 12 20 ns v dd = 5 v 10 15 tphl clk - sdo v dd = 3.3 v 25 40 ns v dd = 5 v 18 25 t on output rise time 10~90 % of voltage waveform v dd = 3.3 v 35 55 ns v dd = 5 v 10 20 t off output fall time 90~10 % of voltage waveform v dd = 3.3 v 4 10 ns v dd = 5 v 3 8 tr clk rise time (3) 5 s tf clk fall time (3) 5 1. all table limits are guaranteed by design. 2. not tested in production. 3. if devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfe r between two cascaded devices.
equivalent circuit and outputs STAP16DPS05 10/34 docid024315 rev 6 4 equivalent circuit and outputs figure 2. oe/dm2 terminal figure 3. le/dm1 terminal figure 4. clk, sdi terminal
docid024315 rev 6 11/34 STAP16DPS05 equivalent circuit and outputs 34 figure 5. sdo terminal figure 6. block diagram -
timing diagrams STAP16DPS05 12/34 docid024315 rev 6 5 timing diagrams note: outn = on when dn = h outn = off when dn = l. figure 7. timing diagram note: latch and output enable are level-sensitive and they are not synchronized with rising or falling edge of clk signal. when le/dm1 terminal is low level, the latch circuits hold the previous set of data. when le/dm1 terminal is high level, the latch circuits refresh new set of data from sdi chain. when oe/dm2 terminal is at low level, the output terminals - out0 to out15 respond to data in the latch circuits, either '1' on or '0' off. when oe/dm2 terminal is at high level, all output terminals are switched off. table 9. truth table clock le/dm1 oe/dm2 serial-in out0 ............. out7 ................ out15 sdo h l dn dn..... dn - 7..... dn -15 dn - 15 l l dn + 1 no change dn - 14 h l dn + 2 dn + 2..... dn - 5..... dn -13 dn - 13 x l dn + 3 dn + 2..... dn - 5..... dn -13 dn - 13 x h dn + 3 off dn - 13
docid024315 rev 6 13/34 STAP16DPS05 timing diagrams 34 figure 8. clock, serial-in, serial-out
timing diagrams STAP16DPS05 14/34 docid024315 rev 6 figure 9. clock, serial-in, latch, enable, outputs figure 10. outputs le/dm1 oe/dm2 outn outn
docid024315 rev 6 15/34 STAP16DPS05 typical characteristics 34 6 typical characteristics figure 11. output current-r ext resistor table 10. output current-r ext resistor r ext ( ) output current (ma) 976 20 780 25 652 30 560 35 488 40 433 45 389 50 354 55 325 60 300 65 278 70 259 75 241 80 229 85 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 iset (ma) rext (ohm) am13674v1
typical characteristics STAP16DPS05 16/34 docid024315 rev 6 conditions: ? temperature = 25 c, v dd = 3.3 v; 5.0 v, i set = 3 ma; 5 ma; 10 ma; 20 ma; 50 ma; 80 ma. figure 12. i set vs. dropout voltage (v drop ) table 11. i set vs. dropout voltage (v drop ) iout (ma) avg @ 3.0 v avg @ 5.0 v 3 19.33 22.66 5 36.67 40.33 10 77.33 80 20 158.67 157.33 50 406 406 80 692 668 am13675v1 0 100 200 300 400 500 600 700 800 0 20406080 iset ma ) vdrop (mv) avg @ 3.0v avg @ 5.0v
docid024315 rev 6 17/34 STAP16DPS05 typical characteristics 34 figure 13. i dd on/off am13676v1 0 2 4 6 8 10 12 14 0 102030405060708090 iset (ma ) idd (ma) iddon avg @ 5.5v iddon avg @ 3.6v iddoff avg @ 5.5v iddoff avg @ 3.6v
detection mode functionality STAP16DPS05 18/34 docid024315 rev 6 7 detection mode functionality 7.1 phase one: ?entering in detection mode? from the ?normal mode? condition the device can switch to the ?error mode? by a logic sequence on the oe/dm2 and le/dm1 pins as shown in the following table and diagram: after these five clk cycles the device goes into the ?error detection mode? and at the 6 th rising edge of clk the sdi data are ready for sampling. table 12. entering in detection truth table clk12345 oe/dm2 hlhhh le/dm1 lllhl figure 14. entering in detection timing diagram am13677v1
docid024315 rev 6 19/34 STAP16DPS05 detection mode functionality 34 7.2 phase two: ?error detection? the 16 data bits must be set to ?1? in order to set on all the outputs during the detection. the data are latched by le/dm1 and after that the outputs are ready for the detection process. when the microcontroller switches the oe/dm2 to low, the device drives the leds in order to analyze if an open or short condition has occurred. the led status is detected at least in 1 microsecond (minimum) and after this time the microcontroller sets oe/dm2 in high state and the output data detection result goes to the microprocessor via sdo. detection mode and normal mode both use the same data format. as soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. to re-detect the status, the device must go back in normal mode and re-enter error detection mode. figure 15. detection diagram
detection mode functionality STAP16DPS05 20/34 docid024315 rev 6 figure 16. timing example for open and/or short detection
docid024315 rev 6 21/34 STAP16DPS05 detection mode functionality 34 7.3 phase three: ?resuming to normal mode? the sequence for re-entering in normal mode is shown in the following table and diagram: note: for proper device operation the ?entering in detection? sequence must be followed by a ?resume mode? sequence, it is not possible to insert consecutive equal sequences. 7.4 error detection conditions v dd = 3.3 to 5 v temperature range -40 to 125 c note: where: i o = the output current programmed by the r ext , i odec = the detected output current in detection mode. figure 17. resuming to normal mode timing diagram clk12345 oe/dm2 hlhhh le/dm1 lllll table 13. detection conditions configuration detection mode detection results sw-1 or sw-3b open line or output short to gnd detected ==> i odec 0.5 x i o no error detected ==> i odec 0.5 x i o sw-2 or sw-3a short on led or short to v-led detected ==> v o 2.4 v no error detected ==> v o 2.2 v
detection mode functionality STAP16DPS05 22/34 docid024315 rev 6 figure 18. detection circuit am13669v1 1 1 6 STAP16DPS05
docid024315 rev 6 23/34 STAP16DPS05 detection mode functionality 34 figure 19. error detection sequence typical schematic used to perform the error detection: figure 20. error detection typical schematic i odec can be measured as follows: i odec = (vled-vload) / rload ta ble 14 and tab le 15 show respectively the i odec average value at 3.3 v and 5.0 v. the i odec is the current value recognized by the device output open error detection. le/dm1 and oe/dm2 key sequence necessary to enter in edm 16 clk pulse are required to load the data setting 1 into shift register the le/dm1 pulse latch the data loaded during the previous state during the error detection are necessary at least 2 clk signal plus oneat the end every clk pulse shows the results of single output results:out15;14; 13 etc. etc after oe/dm2 signal turn high the the device from edm to normal mode 16 clk pulse are required to load the data setting 1 into shift register during the error detection are necessary at least 2 clk signal plus oneat the end every clk pulse shows the results of single output results:out15;14; 13 etc. etc sdo pin show the results of error detection (open or short in this case) the oe/dm2 pulse put the device from edm to normal mode am13678v1 dut vled rload i dec out r ext iset vdd gnd
detection mode functionality STAP16DPS05 24/34 docid024315 rev 6 table 14. i odec average value at 3.3 v vdd (v) iset (ma) r ext ( ) iout avg (ma) 3.3 542702.097 10 2056 6.79 20 1006 10.46 50 382 26.92 80 251 35.03 table 15. i odec average value at 5 v vdd (v) iset (ma) r ext ( ) iout avg (ma) 5 542701.98 10 2056 6.09 20 1006 9.67 50 382 25.54 80 251 38.9
docid024315 rev 6 25/34 STAP16DPS05 detection mode functionality 34 7.5 auto power-saving the auto power-saving feature minimizes the quiescent current if no active data is detected on the latches and auto powers-up the device as the first active data is latched. figure 21. auto power-saving feature conditions: ? temp. = 25 c, v dd = 3.3 v, vin = v dd , vled = 3.0 v, iset = 20 ma ? ch1 (yellow) = i dd , ch2 (blue) = sdi, ch3 (purple) = le/dm1, ch4 (green) = clk idd consumption: ? idd (normal operation) = 5.15 ma ? idd (shutdown condition) = 163 a am13679v1
detection mode functionality STAP16DPS05 26/34 docid024315 rev 6 figure 22. delay le-out after 16 clock cycles without data change, the auto power-saving mode starts as expected. delay tle-out = 1.053 s conditions: ? temp. = 25 c, v dd = 3.3 v, vin = v dd , vled = 3.0 v, iset = 20 ma ? ch1 (yellow) = clk, ch2 (blue) = sdi, ch3 (purple) = le/dm1, ch4 (green) = iout am13680v1
docid024315 rev 6 27/34 STAP16DPS05 detection mode functionality 34 figure 23. auto power-saving behavior note: when the device goes from auto power-saving to normal operating condition, the first output switching on shows the t on condition as seen in the plot above. temp. = 25c, v dd = 3.3 v, vin = v dd , vled = 3.0 v, iset = 20 ma ch1 (yellow) = idd, ch2 (blue) = sdi, ch3 (purple) = le/dm1, ch4 (green) = clk. am13681v1
package information STAP16DPS05 28/34 docid024315 rev 6 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid024315 rev 6 29/34 STAP16DPS05 package information 34 8.1 tssop24 exposed pad package information figure 24. tssop24 exposed pad package outline 7100778_d
package information STAP16DPS05 30/34 docid024315 rev 6 table 16. tssop24 exposed pad mechanical data symbol mm min. typ. max. a 1.20 a1 0.15 a2 0.80 1.00 1.05 b0.19 0.30 c0.09 0.20 d 7.70 7.80 7.90 d1 4.80 5.00 5.2 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e2 3.00 3.20 3.40 e0.65 l 0.45 0.60 0.75 l1 1.00 k0 8 aaa 0.10
docid024315 rev 6 31/34 STAP16DPS05 package information 34 8.2 tssop24 exposed pad packing information figure 25. tssop24 exposed pad tape and reel outline
package information STAP16DPS05 32/34 docid024315 rev 6 table 17. tssop24 exposed pad tape and reel mechanical data dim. mm min. typ. max. a 330 c 12.8 13.2 d 20.2 n 60 t 22.4 ao 6.8 7 bo 8.2 8.4 ko 1.7 1.9 po 3.9 4.1 p 11.9 12.1
docid024315 rev 6 33/34 STAP16DPS05 revision history 34 9 revision history table 18. document revision history date revision changes 21-may-2013 1 initial release. 01-jul-2013 2 added footnote in table 8: switching characteristics. 11-oct-2013 3 modified t opr value in table 4: absolute maximum ratings. 10-mar-2014 4 modified footnote 1 in table 8: switching characteristics. added footnote 2 in table 8: switching characteristics. updated table 3: pin description. 05-jun-2014 5 updated table 16: tssop24 exposed pad mechanical data. minor text changes. 10-nov-2015 6 updated features in cover page. minor text changes.
STAP16DPS05 34/34 docid024315 rev 6 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STAP16DPS05

	To Download STAP16DPS05 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .